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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16315-1E
32-bit Proprietary Microcontrollers
CMOS
FR30 Series
MB91126
s DESCRIPTION
This model is a standard single-chip microcontroller with the 32-bit RISC CPU (FR30 family) as its core, incorporating a variety of I/O resources and bus control features for embedded control applications which require highspeed CPU processing. With 10 KB of built-in RAM, the microcontroller is best suited for applications which require high-level CPU processing capabilities, such as navigation systems, high-performance FAX, and printer controllers.
s FEATURES
FR-CPU * 32-bit RISC (FR30), load/store architecture with a five-stage pipeline * Operating frequency: Internal 25 MHz * General purpose registers: 32 bits x 16 registers * 16-bit fixed-length instructions (basic instructions): One instruction per cycle * Memory-to-memory transfer, bit processing, and barrel shift instructions: Instructions suitable for embedded control applications * Function entrance/exit instructions and register data multi-load/store instructions: Instructions applicable to high-level languages (Continued)
s PACKAGE
100-pin Plastic LQFP
(FPT-100P-M05)
MB91126
* Register interlock functions: Facilitating coding in assemblers * Branch instructions with delay slot: Reducing the overhead in branching * Internal multiplier/supported at the instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles * Interrupt (saving PC and PS): 6 cycles, 16 priority levels Bus interface * Internal 25 MHz * 25-bit address bus (32 MB space) * 16-bit address output, 8-/16-bit data input/output * Basic bus cycle : 2-clock cycle * Chip select output that can be set to a minimum 64-Kbyte units : 6 * Interface support for various memories DRAM interface (Area 4 and 5) * Automatic wait cycle insertion: Flexible setting, from 0 to 7 cycles per area * Unused data/address pins can be configured as input/output ports. * Little endian mode supported (One area selected from among area 1 to 5) DRAM Interface * Independent control of two banks (area 4 and 5) * Double CAS DRAM (normal DRAM I/F)/Single CAS DRAM/Hyper DRAM * Basic bus cycles: Normally 5 cycles. 2-cycle enabled in Fast Page mode. * Programmable waveform: Capable of automatic insertion of one wait cycle to RAS and CAS * DRAM refresh CBR refresh (Arbitrary interval setting using a 6-bit timer) Self-refresh mode * 8/9/10/12-bit column addresses supported * 2CAS/1WE or 2WE/1CAS selectable DMAC (DMA controller) * 8 channels * Transfer incident: External pin/internal resource interrupt requests * Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer * Transfer data length: 8, 16, or 32 bits selectable * Capable of pausing with an NMI/interrupt request UART * 3 channels * Full duplex double buffer * Data length 7 bits to 9 bits (without parity) , 6 bits to 8 bits (with parity) * Asynchronous (start-stop system) or CLK-synchronized communication selectable * Multi processor mode * Internal 16-bit timer (U-Timer) as a baud rate generator: Generates any given baud rate. * Capable of using an external clock as the transfer clock * Error detection: Parity, frame, and overrun
(Continued)
2
MB91126
(Continued)
Reload Timer * 16-bit timer : 3 channels * Internal clock : 2-clock resolution, 2, 8 or 32 divide and external clock can be selected. Other interval timer * 16-bit timer : 3 channels (U-Timer) * Watchdog timer: 1 channel Built-in RAM 10 KB * D-bus RAM 8 KB, C-bus RAM 2KB Bit Search Module * Searching the MSB in one word for the first 1/0 change bit position Interrupt Controler * External interrupt input : NMI, normal interrupt x 6 (INT0 to INT5) * Internal interrupt sources : UART, DMAC, reload timer, UTIMER, delay interrupt * Priority levels are programmable except for NMI (16 levels) . Reset Source * Power-on reset/watchdog timer/softwere reset/external reset Low Power Consumption Mode * Sleep/stop mode Clock control * Built-in PLL circuit: PLL multiplication factor selectable from among 1, 1.5, and 2 * Gear function: Capable of freely setting different operating clock frequencies for the CPU and peripherals Gear clock selectable from among 1/1, 1/2, 1/4, and 1/8 (or among 1/2, 1/4, 1/8, and 1/16). Note, however, that peripherals operate at a maximum of 25 MHz. Others * Package : LQFP-100 * CMOS technology : 0.35 m * Power supply voltage : 3.3 V 0.3 V
s PRODUCT LINEUP
Part number Description FLASH Memory D-bus RAM C-bus RAM MB91126 For mass production 8 KB 2 KB MB91FV129 For evaluation 510 KB 16 KB 2 KB
3
MB91126
s PIN ASSIGNMENT
(TOP VIEW)
PB4/RAS1/EOP2 PB3/DW0 PB2/CS0H PB1/CS0L PB0/RAS0 PE0/INT0 PE1/INT1 VCC X0 X1 VSS PE2/INT2/SC1 PE3/INT3/SC2 PE4/DREQ0 PE5/DREQ1 PE6/DACK0 PE7/DACK1 PF7/INT4 PF6/SO2 PF5/SI2 PF4/SO1 PF3/SI1 PF2/SC0 PF1/SO0 PF0/SI0 PB5/CS1L/DREQ2 PB6/CS1H/DACK2 PB7/DW1 VCC PA6/CLK PA5/CS5 PA4/CS4 PA3/CS3/EOP1 PA2/CS2 PA1/CS1 PA0/CS0 NMI HST RST VSS MD0 MD1 MD2 P80/RDY P81/BGRNT P82/BRQ P83/RD P84/WR0 P85/WR1 P20/D16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PD3/INT5 PD2 PD1 PD0 VSS VCC VCC P70/A24/EOP0 P67/A23 P66/A22 VSS P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A09 P50/A08
4
P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 VSS P37/D31 P40/A00 VCC P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07
(FPT-100P-M05)
MB91126
s PIN DESCRIPTIONS
Note that the numbers in the table are not pin numbers on a package. I/O circuit NO. Pin name Function type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24/P30 D25/P31 D26/P32 D27/P33 D28/P34 D29/P35 D30/P36 D31/P37 A00/P40 A01/P41 A02/P42 A03/P43 A04/P44 A05/P45 A06/P46 A07/P47 A08/P50 A09/P51 A10/P52 A11/P53 A12/P54 A13/P55 A14/P56 A15/P57 A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67
D
These pins use bit 16 to bit 23 of the external data bus. They can be used as ports (P20 to P27) if the external bus width is 8 bits or in single chip mode.
D
These pins use bit 24 to bit 31 of the external data bus. They can serve as general purpose I/O pins (P30 to P37) when unassigned.
D
These pins use bit 00 to bit 15 of the external address bus. They can be used as general purpose I/O ports (P40 to P47, P50 to P57) when not used as address bus.
D
These pins use bits 16 to 23 of the external data bus. They can be used as general purpose I/O ports (P60 to P67) when not used as address bus.
(Continued)
5
MB91126
NO.
Pin name
I/O circuit type
Function Bit 24 of the external address bus. Enabled when the DMAC EOP output is enabled. [P70] A24 can be used as a general purpose I/O port when EOP0 is not used. [EOP0] DMAC EOP0 output (ch0) External ready input. This pin inputs 0 when the bus cycle being executed is not completed. It can serve as a general purpose I/O port when unassigned. External bus release acknowledge output. This pin outputs the "L" level when the external bus is released. It can serve as a general purpose I/O port when unassigned. External bus release request input. This pin inputs 1 when the external bus is required to be released. It can serve as a general purpose I/O port when unassigned. External bus read strobe. It can serve as a general purpose I/O port when unassigned. External bus write strobe. Control signals and data bus byte positions have the following relationships:
16-bit bus width D31 to D24 D23 to D16 WR0 WR1 8-bit bus width WR0 Single chip mode
41
A24/P70/EOP0
D
42
RDY/P80
D
43
BGRNT/P81
D
44
BRQ/P82
D
45 46
RD/P83 WR0/P84
D D
(port enabled) (port enabled)
(port enabled)
47
WR1/P85
D Notes : WR1 remains in High-Z state during a reset. For use at a 16-bit bus width, add an external pull-up resistor. [P84 or P85] WR0 can be used as a general purpose I/O port when WR1 is not used.
48 49 50
CS0/PA0 CS1/PA1 CS2/PA2
D
Chip select 0 output (Low active) Chip select 1 output (Low active) Chip select 2 output (Low active) [PA0, 1, 2] They can serve as general purpose I/O ports when unassigned. Chip select 3 output (Low active) [EOP1] DMAC EOP output (ch1) This funcyion is valid when DMAC and EOP output are enabled. [PA3] It can serve as a general purpose I/O port when CS3 and EOP1 are unassigned. Chip select 4 output (Low active) Chip select 5 output (Low active) [PA4, 5] They can serve as general purpose I/O ports when unassigned. System clock output Outputs clock signal of external bus operating frequency. [PA6] It can serve as a general purpose I/O port when unassigned.
51
CS3/PA3/ EOP1
D
52 53
CS4/PA4 CS5/PA5
D
54
CLK/PA6
D
(Continued)
6
MB91126
NO.
Pin name
I/O circuit type
Function RAS output of DRAM bank 0 CASL output of DRAM bank 0 CASH output of DRAM bank 0 WE output of DRAM bank 0 (Low active) RAS output of DRAM bank 1 CASL output of DRAM bank 1 CASH output of DRAM bank 1 WE output of DRAM bank 1 (Low active) In detail, refer to "DRAM interface". [EOP2] DMAC EOP output (ch2). This function is enabled when the DMAC EOP output is enabled. [DREQ2] DMA external transfer request input. Since this input is used as required when it has been selected as a DMAC transfer trigger event, the output by the other function must remain off unless used intentionally. [DACK2] DMAC external transfer request accept output (ch2). This function is enabled when the DMAC transfer request accept output is enabled. [PB0 to PB7] Available as general purpose I/O ports when unassigned. Mode pins 0 to 2. These pins set the basic operation mode of the MCU. Connect the pins directly to VCC or VSS. Clock (oscillation) input Clock (oscillation) output External reset input Hardwere standby input NMI (Non Maskable Interrupt) input (Low Active) [INT0, 1] These are external interrupt request inputs. This input is always used while the corresponding external interrupt is permitted, so output using other functions should be stopped except when carried out intentionally. [PE0,PE1]General purpose I/O ports [INT2] These are external interrupt request inputs. This input is always used while the corresponding external interruption is permitted, so output using other functions should be stopped except when carried out intentionally. [PE2] General purpose I/O port This function is effective if clock output specification of UART1 is pohibited. [SC1] UART1 clock input/output Clock output is effective if clock output specification of UART1 is permitted.
55 56 57 58 59 60 61 62
RAS0/PB0 CS0L/PB1 CS0H/PB2 DW0/PB3 RAS1/PB4/EOP2 CS1L/PB5/DREQ2 CS1H/PB6/DACK2 DW1/PB7
D
63 64 65 66 67 68 69 70
MD0 MD1 MD2 X0 X1 RST HST NMI
B
A C C C
71 72
INT0/PE0 INT1/PE1
D 73 INT2/PE2/SC1
(Continued)
7
MB91126
NO.
Pin name
I/O circuit type
Function [INT3] These are external interrupt request inputs. This input is always used while the corresponding external interrupt is permitted, so output using other functions should be stopped except when carried out intentionally. [SC2] UART2 clock input/output Clock output is effective if clock output specification of UART2 is permitted. [PE3]General purpose I/O port This function is effective if clock output specification of UART2 is pohibited. [PE4,PE5]General purpose I/O ports [DREQ0, 1] These are DMA external interrupt transfer request inputs. This input is always used if selected as the transfer factor for DMAC, so outputs from other functions should be stopped except when carried out intentionally. [PE4,PE5]General purpose I/O ports
74
INT3/PE3/SC2
D
75 76
DREQ0/PE4 DREQ1/PE5 D
77
DACK0/PE6
[DACK0] This is the DMAC external transfer request accept output (ch 0) . This function is effective if the transfer request accept output specification of DMAC is prohibited. [PE6]General purpose I/O port This function is effective if the transfer request accept output specification of DMAC or DACK0 is prohibited. [DACK1] This is the DMAC external transfer request accept output (ch 1) . This function is effective if the transfer request accept output specification of DMAC is prohibited. [PE7]General purpose I/O port This function is effective if the transfer request accept output specification of DMAC or DACK1 is prohibited. [SI0] UART0 data input This input is always used while UART inputs, so outputs from other functions should be stopped except when carried out intentionally. [PF0]General purpose I/O port [SO0] UART0 data input This function is effective if the UART0 data output specification is permitted. [PF1]General purpose I/O port This function is effective if data output specification of UART0 is pohibited. [SC0] UART0 clock output Clock output is effective if the UART0 clock output specification is permitted. [PF2]General purpose I/O port This function is effective if clock output specification of UART0 is prohibited. [SI1] UART1 data input This function is always used if selected as the initiation factor for A/D, so output by other functions should be stopped except when it is carried out intentionally. [PF3]General purpose I/O port
78
DACK1/PE7 D
79
SI0/PF0
80
SO0/PF1
D
81
SC0/PF2
D
82
SI1/PF3
D
(Continued)
8
MB91126
(Continued)
NO. Pin name I/O circuit type Function [SO1] UART1 data output This function is effective if data output specification of UART1 is permitted. [PF4]General purpose I/O port This function is effective if data output specification of UART1 is prohibited. [SI2] UART2 data input This function is always used if selected as the initiation factor for A/D, so output by other functions should be stopped except when it is carried out intentionally. [PF5]General purpose I/O port [SO2] UART2 data input This function is effective if data output specification of UART1 is permitted. [PF6] General purpose I/O port This function is effective if data output specification of UART1 is prohibited. [INT4] External interrupt request input This function is always used if selected as the initiation factor for A/D, so output by other functions should be stopped except when it is carried out intentionally. [PF7] General purpose I/O port [PD0 to PD2] General purpose I/O ports [PD3]General purpose I/O port [INT5] External interrupt request input This function is always used if selected as the initiation factor for A/D, so output by other functions should be stopped except when it is carried out intentionally. This provides power for the circuit system. Always power supply pin (VCC) must be connected to the power supply. This is the earth level for digital circuits.
83
SO1/PF4
D
84
SI2/PF5
D
85
SO2/PF6
D
86
INT4/PF7
D
87 to 89
PD0 PD1 PD2
E
90
PD3/INT5
E
91 to 95 96 to 100
VCC VSS

Note : The I/O port and resource input/outputs for most of the above pins are multiplexed, i.e. Pxx/xxxx. In the event of both the port and resource outputs were to use the same pins, the resource is given priority.
9
MB91126
s I/O CIRCUIT TYPE
Type
X1
Circuit
Clock input
Remarks
A
X0 STANDBY
For 25 MHz Oscillation feedback resistor : approx. 1 M Standby control OFF
* CMOS level input. * With high voltage control for FLASH test B
Control signal Mode input Diffused resistor
* CMOS level, hysteresis input. * Standby control OFF
P-channel transistor N-channel transistor
C
Diffused resistor Digital input CMOS
Digital output
* CMOS level output * CMOS level, hysteresis input. * Standby control ON
D
Diffused resistor
Digital output
STANDBY
Digital input
Digital output
* * * *
Standby control ON CMOS level output CMOS level, hysteresis input. Analog input
E
Diffused resistor
Digital output
Analog input STANDBY Digital input
10
MB91126
s HANDLING DEVICES
1. Preventing Latch-up
The latch-up phenomenon may be generated if a voltage in excess of VCC or lower than VSS is applied to the input/output pins, or if the voltage exceeds the rating between VCC and VSS. If latch-up is generated, the electrical current increases significantly and may destroy certain components due to the excessive heat, so great care must be taken to ensure that the maximum rating is not exceeded during use. Also, care must be taken to ensure that the analog pin does not exceed the digital power supply.
2. Treatment of Pins
* Handling Unused Input Pins Input pins that are not used should be pulled up or down as they may cause erroneous operations if they are left open. * Crystal Oscillator Circuit Noise around the X0 or X1 pins may cause erroneous operation. Make sure to provide bypass capacitors via shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuits not cross the lines of other circuit. A printed circuit board artwork surrounding the X0 and X1 pins with ground area for stabilizing the operation is highly recommended . * N.C. Pins N.C. pin must be opened for use. * Mode Pins (MD0 to MD2) Those pins must be directly connected to VCC or VSS for use. Pattern length between VCC or VSS and each mode pin on the printed-circuit board should be arranged to be as short as possible to prevent the test mode being erroneously turned on due to noise, they should also be connected with low impedance.
3. Precautions
* External Reset Input "L" level should be input to the RST pin, which is required for at least five machine cycles to ensure the internal status is reset. * Notes on Using External Clock If external clock is used, X0 pin should be provided, and X1 pin should be provided with reverse phase to X0 pin. However, in this case, do not use the STOP mode (oscillation stop mode) . (At STOP, the X1 pin is stopped with the "H"). Under a 12.5 MHz frequency, the device operates with a clock supplied to X0 terminal only. Examples of the external clock usage methods is shown below. Example of Using external clock (normal)
X0 X1
Note : It cannot use in the STOP mode (oscillation stop mode) .
11
MB91126
Example of Using external clock (enable to using less than 12.5 MHz)
X0 OPEN X1
* Power Supply Pins (VCC, VSS) In products with multiple Vcc or Vss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect Vcc and Vss pins via the lowest impedance to power lines.
4. Care During Power Up
* Power-on The RST pin must be started from "L" level when the power is turned on, and when the power is adjusted to the VCC level it should be changed to the "H" level after being left for at least five cycles of the internal operation clock. * Pin condition at the power-on The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on the power supply and then starting oscillation. * Original Oscillation Input in the Event that Power Is Turned on The clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on. * Initialization of power-on reset In the device, there are internal registers which is initialized only by a power-on reset. To initialize these resistors, run power-on reset by returning on the power supply. * Recovery for sleep/stop For recovering from sleep/stop status initiated by a program in C-Bus RAM, reset the device instead of recovering by an interrupt process.
5. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
12
MB91126
s BLOCK DIAGRAM
FR CPU D-bus (32 bits) I-bus (16 bits)
RAM (8 Kbytes) Bit search module DREQ0 to DREQ2 DACK0 to DACK2 EOP0 to EOP2 3 3 3 DMA controller (8 ch.)
Bus converter (Harvard---Princeton) 16 25 Bus controller C-bus (32 bits) 2
Bus converter (32 bits---16 bits)
X0 X1 RST HST INT0 to INT5 NMI SI0 to SI2 SO0 to SO2 SC0 to SC2 6
Clock control unit (Watchdog timer)
6
Interrupt control unit R-bus (16 bits) 3 3 3
D16 to D31 A00 to A24 RD WR0, WR1 RDY CLK BRQ BGRNT CS0 to CS5 RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1
UART (3 ch)
DRAM controller
Reload timer (3 ch)
Port0 to portB
Port D, E, F
RAM (2 Kbytes)
Notes : * Pins are described per function. Some of the pins are multiplexed. * In the event that REALOS is used, an external interruption or built-in timer should be used to control the time.
13
MB91126
s MEMORY MAP
The memory space of MB91126 is shown.
External ROM External bus mode
0000 0000H I/O 0000 0400H I/O 0000 0800H 0000 1000H
Internal ROM External bus mode Direct addressing area I/O Map (See Appendix A)
I/O
I/O
Access prohibited
Access prohibited
Internal RAM 8 KB
0000 3000H
Internal RAM 8 KB
Access prohibited
0001 0000H
Access prohibited
0001 0000H
External area
0008 0000H
Internal RAM 2 KB External area
Access prohibited
0008 0800H
0010 0000H
External area
FFFF FFFFH FFFF FFFFH
Note : External area is not accessible in single-chip mode. When accessing to external areas, select the internal ROM external bus mode in mode register. Direct addressing area The following areas of the address space are used for I/O. This area is called the "direct addressing area" and the address of the operand can be specified directly during instruction. The direct area differs depending on data size to be accessed. * Byte data access : 0 to 0FFH * Half word data access : 0 to 1FFH * Word data access : 0 to 3FFH
14
MB91126
s HOW TO READ I/O MAP
address 000000H Register +0 PDR3 [R/W] XXXXXXXX +1 PDR2 [R/W] XXXXXXXX +2 -------+3 -------Internal resource Port Data Register
Read/write attribute Initial register value after reset Register name (the register listed in the first column is at address 4n, the register listed in the second column is at address 4n + 1, - - - ) Leftmost register address (the first column register is on the MSB side of data in word access mode)
Note : Register bit value indicate initial values as shown below. "1" : Initial value "1" "0" : Initial value "0" "X" : Initial value "X" "-" : Register does not exist physically in this position.
15
MB91126
s I/O MAP
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H SSR [R/W] 00001- 00 SSR [R/W] 00001- 00 SSR [R/W] 00001- 00 PDRD [R/W] - - - - XXXX SIDR [R/W] XXXXXXXX SIDR [R/W] XXXXXXXX SIDR [R/W] XXXXXXXX Register +0 PDR3 [R/W] XXXXXXXX PDR7 [R/W] -------X PDRB [R/W] XXXXXXXX +1 PDR2 [R/W] XXXXXXXX PDR6 [R/W] XXXXXXXX PDRA [R/W] XXXXXXXX PDRE [R/W] XXXXXXXX SCR [R/W] 00000100 SCR [R/W] 00000100 SCR [R/W] 00000100 PDRF [R/W] XXXXXXXX SMR [R/W] 00 - - 0 - 00 SMR [R/W] 00 - - 0 - 00 SMR [R/W] 00 - - 0 - 00 Reserved UART0 UART1 UART2 +2 PDR5 [R/W] XXXXXXXX +3 PDR4 [R/W] XXXXXXXX PDR8[R/W] - - XXXXXX Port data register Internal resources
TMRLR [W] XXXXXXXX XXXXXXXX TMRLR [W] XXXXXXXX XXXXXXXX TMRLR [W] XXXXXXXX XXXXXXXX
TMR [W] XXXXXXXX XXXXXXXX TMCSR [R/W] - - - - 0000 00000000 TMR [W] XXXXXXXX XXXXXXXX TMCSR [R/W] - - - - 0000 00000000 TMR [W] XXXXXXXX XXXXXXXX TMCSR [R/W] - - - - 0000 00000000
Reload timer 0
Reload timer 1
Reload timer 2
Reserved
(Continued)
16
MB91126
Address 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H
Register +0 UTM/UTIMR [R/W] 00000000 00000000 UTM/UTIMR [R/W] 00000000 00000000 UTM/UTIMR [R/W] 00000000 00000000 EIRR [R/W] 00000000 EHVR [R/W] - - - - 0000 ENIR [R/W] 00000000 ELVR [R/W] 00000000 DDRD [W] - - - - 0000 DDRE [W] 00000000 DDRF [W] 00000000 +1 +2 UTIMC[R/W] 0 - - 00001 UTIMC[R/W] 0 - - 00001 UTIMC[R/W] 0 - - 00001 +3
Internal resources
Reserved
U-timer 0 U-timer 1 U-timer 2 Reserved Reserved
External interrupt /NMI
Reserved
Port direction register
(Continued)
17
MB91126
Address 0000D8H 0000DCH to 0000FCH 000100H to 0001FCH 000200H 000204H 000208H 00020CH 000210H to 0002FCH 000300H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H
Register +0 +1 +2 +3
Internal resources Reserved Reserved
DPDP [R/W] - - - - - - - - - - - - - - - - - - - - - - - - -0000000 DACSR [R/W] 00000000 00000000 00000000 00000000 DATCR [R/W] - - - - - - - - - - XX0000 - - XX0000 - - XX0000
Reserved
DMAC
Reserved
BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICR00 [R/W] - - -11111 ICR04[R/W] - - -11111 ICR08 [R/W] - - -11111 ICR12[R/W] - - -11111 ICR16[R/W] - - -11111 ICR01[R/W] - - -11111 ICR05[R/W] - - -11111 ICR09[R/W] - - -11111 ICR13[R/W] - - -11111 ICR17[R/W] - - -11111 ICR02[R/W] - - -11111 ICR06[R/W] - - -11111 ICR10[R/W] - - -11111 ICR14[R/W] - - -11111 ICR18[R/W] - - -11111 ICR03[R/W] - - -11111 ICR07[R/W] - - -11111 ICR11[R/W] - - -11111 ICR15[R/W] - - -11111 ICR19[R/W] - - -11111
Reserved
Bit search module
Interrupt controller
(Continued)
18
MB91126
Address 000414H 000418H 00041CH 000420H 000424H 000428H 00042CH 000430H 000434H to 00047CH 000480H
Register +0 ICR20[R/W] - - -11111 ICR24 [R/W] - - -11111 ICR28[R/W] - - -11111 DICR [R/W] -------0 +1 ICR21[R/W] - - -11111 ICR25[R/W] - - -11111 ICR29[R/W] - - -11111 HRCL [R/W] - - -11111 RSRR/WTCR [R/W] 1XXXX- 00 GCR [R/W] 110011 - 1 PTCR [R/W] 00 - - 0 - - DDR3 [W] 00000000 DDR7 [W] -------0 DDRB [W] 00000000 DDR2 [W] 00000000 DDR6 [W] 00000000 DDRA [W] -0000000 DDR5 [W] 00000000 DDR4 [W] 00000000 DDR8 [W] - - 000000 STCR [R/W] 000111- WPR [W] XXXXXXXX PDDR [R/W] - - - - 0000 CTBR [W] XXXXXXXX +2 ICR22[R/W] - - -11111 ICR26[R/W] - - -11111 ICR30[R/W] - - -11111 +3 ICR23[R/W] - - -11111 ICR27[R/W] - - -11111 ICR31[R/W] - - -11111 ICR47[R/W] - - -11111
Internal resources
Interrupt controller
Delay interruption
Reserved
Clock control block
000484H 000488H 00048CH to 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H
PLL control block
Reserved
Data direction register
ASR1 [W] 00000000 00000001 ASR2 [W] 00000000 00000010 ASR3 [W] 00000000 00000011 ASR4 [W] 00000000 00000100
AMR1 [W] 00000000 00000000 AMR2 [W] 00000000 00000000 AMR3 [W] 00000000 00000000 AMR4 [W] 00000000 00000000
External bus interface
(Continued)
19
MB91126
(Continued)
Address 00061CH 000620H 000624H 000628H 00062CH 000630H to 0007BCH 0007C0H 0007C4H to 0007F8H 0007FCH LER [W] - - - - - 000 MODR [W] XXXXXXXX Register +0 +1 +2 +3 ASR5 [W] 00000000 00000101 AMD0 [R/W] - - - XX111 AMD5[R/W] 0 - - 00000 AMD1 [R/W] 0 - - 00000 DSCR [W] 00000000 AMR5 [W] 00000000 00000000 AMD32[R/W] 00000000 AMD4 [R/W] 0 - - 00000 External bus interface Internal resources
RFCR [R/W] --XXXXXX 00 - - - 000 EPCR1 [W] - - - - - - - 1 11111111 DMCR5 [R/W] 00000000 0000000
EPCR0 [W] - - 1 - 1100 -1111111 DMCR4 [R/W] 00000000 0000000-
Reserved Reserved Reserved Little endian register mode register
Note : Do not execute RMW instructions to registers with write-only bits. RMW instruction (RMW : Read/Modify/Write) AND Rj, @Ri OR Rj, @Ri EOR Rj, @Ri ANDH Rj, @Ri ORH Rj, @Ri EORH Rj, @Ri ANDB Rj, @Ri ORB Rj, @Ri EORB Rj, @Ri BANDL #u4, @Ri BORL #u4, @Ri BEORL #u4, @Ri BANDH #u4, @Ri BORH #u4, @Ri BEORH #u4, @Ri Data in "Reserved" or "" is undecided.
20
MB91126
s INTERRUPT VECTOR
Interrupt source Reset System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation Exceptions to undefined instruction NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 UART 0 reception completed UART1 reception completed UART2 reception completed UART0 transmission completed UART1 transmission completed UART2 transmission completed DMAC 0 (end, error) DMAC 1 (end, error) DMAC 2 (end, error) DMAC 3 (end, error) DMAC 4 (end, error) DMAC 5 (end, error) DMAC 6 (end, error) DMAC 7 (end, error) System reservation IInterrupt number Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Hexadecimal
Interrupt level *1 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18
Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H 374H
Address of TBR default*2 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22
(Continued)
21
MB91126
(Continued)
IInterrupt number Interrupt source Reload timer 0 Reload timer 1 Reload timer 2 External interrupt 4 External interrupt 5 System reservation System reservation U-TIMER 0 U-TIMER 1 U-TIMER 2 System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation Delay interrupt source bit System reservation (used under REALOS) *3 System reservation (used under REALOS) *3 Used under INT instruction Decimal 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 to 255 Hexadecimal 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 to FF Interrupt level *1 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 Offset 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H to 000H Address of TBR default*2 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H to 000FFC00H
22
MB91126
*1 : ICRs are registers in the interrupt controller that set the interrupt levels for individual interrupt requests. An ICR is provided for each interrupt request. *2 : The TBR is the register that holds the start address of the EIT vector table. The address obtained by adding the offset value defined for each EIT to the TBR value is used as the vector address. *3 : When REALOS/FR is used, 0x40 and 0x41 interrupts are used for system code.
Reference : The EIT vector area is one kilobyte long starting at the address held in the TBR. The size for each vector is four bytes. Vector numbers and vector addresses have the following relationships: vctadr = TBR + vctofs = TBR + ( 3FC H - 4 x vct) vctadr : vector address, vctofs : vector offset, vct : vector number
23
MB91126
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature Symbol VCC VI VO ICLAMP | ICLAMP | IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV Pd Ta Tstg Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 - 30 - 55 Max VSS + 4.0 VCC + 0.3 VCC + 0.3 + 2.0 20 10 4 100 50 - 10 -4 - 50 - 20 500 + 70 + 150 Unit V V V mA mA mA mA mA mA mA mA mA mA mW C C *3 *3 *1 *2 *4 *4 *1 *2 (VSS = 0 V) Remarks
*1 : The maximum output current specifies the peak current for the relevant single pin. *2 : The average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *3 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. *4 : * Applicable to pins: P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70, P80 to P85, PA0 to PA6, PB0 to PB7, PD0 to PD3, PE0 to PE7, PF0 to PF7 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. (Continued) 24
MB91126
(Continued) * Sample recommended circuits:
* Input/Output Equivalent circuits
Protective diode
VCC
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
Value Min 3.0 Power supply voltage Operating temperature VCC Ta 2.0 - 30 Max 3.6 3.6 + 70 V C
(VSS = 0 V) Unit Remarks At normal operating Keeping RAM status in the case of stopping
Parameter
Symbol
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
25
MB91126
3. DC Characteristics
Symbol VIHS VILS VOH VOL ILI ICC Power supply current ICCS ICCH Input capacitance CIN Without VCC, VSS VCC
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Pin Condition VCC = 3.3 V IOH = - 4.0 mA VCC = 3.3V IOL = 4.0 mA VCC = 3.6 V VSS < VI < VCC 25 MHz VCC = 3.3 V 25 MHz VCC = 3.3 V Ta = + 25 C VCC = 3.3 V Value Min 0.8 x VCC VSS - 0.3 VCC - 0.5 Typ 75 60 10 10 Max VCC + 0.3 0.2 x Vcc 0.4 5 100 85 150 Unit V V V V A mA mA A pF at sleep mode at stop mode * * Remarks
Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leak current
Hysteresis input pin Hysteresis input pin Port2 to PortF Port2 to PortF Port2 to PortF
* : See "s I/O CIRCUIT TYPE"
26
MB91126
4. AC Characteristics
(1) Clock Timing (VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Symbol Condition Value Min 10 Max 25 Unit MHz Remarks Range in which self oscillation is allowed Range in which self oscillation and external clock input is allowed*1 Range in which external clock input is allowed
Parameter Clock frequency (High-speed * self oscillation) Clock frequency (High-speed * PLL using) Clock frequency (High-speed * 1/2 cycle input) Clock cycle time Input clock pulse width Input clock Rise/fall time Internal operating clock frequency Internal operating clock cycle time CPU system Peripheral CPU system Peripheral
fC
10 10
25
MHz
25 100 8 25 25 1600*2 1600*2
MHz ns ns ns MHz MHz ns ns
tC PWH, PWL tCR tCF fCP fCPP tCP tLCPP
40 9.5 0.625*2 0.625*2 40 40
(tCR + tCF)
*1 : A multiplication factor of 1 or 2 can be selected for the PLL. It is however restricted depending on the operating oscillation frequency. Do not set the PLL multiplication factor to 2 when the oscillation frequency exceeds 12.5 MHz. *2 : This value is obtained when an oscillation circuit divide ratio of 2 and a gear cycle of 1/8 are used with a minimum clock frequency of 10 MHz input to X0.
tC 0.8 VCC 0.2 VCC PWH tcf PWL tcr
27
MB91126
Power supply voltage (V) Operation Assurance Range (Ta = -30 C to +70 C)
3.6
3.0
27
Frequency (MHz)
28
MB91126
(2) Clock Output Timing
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Pin CLK CLK CLK Condition Value Min tCP Max Unit ns ns ns Remarks *1 *2 *3
Parameter Cycle time CLK CLK CLK CLK
Symbol tCYC tCHCL tCLCH
1 / 2 x tCYC - 10 1 / 2 x tCYC + 10 1 / 2 x tCYC - 10 1 / 2 x tCYC + 10
*1 : tCYC is frequency of 1 clock cycle including the gear cycle. *2 : The values assume a gear cycle of x 1. When a gear cycle of 1/2, 1/4, or 1/8 is specified, substitute "n" in the following equations with 1/2, 1/4, 1/8, respectively. Min : (1 - n / 2) x tCYC - 10 Max : (1 - n / 2) x tCYC + 10 *3 : The values assume a gear cycle of x 1. When a gear cycle of 1/2, 1/4, or 1/8 is specified, substitute "n" in the following equations with 1/2, 1/4, 1/8, respectively Min : n / 2 x tCYC - 10 Max : n / 2 x tCYC + 10 Clock output timing
tCYC tCHCL VOH tcLCH VOH VOL
CLK
29
MB91126
(3) Reset Input
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Symbol tRSTL Pin RST Condition Value Min tCP x 5 Max Unit ns Remarks
Parameter Reset input time
tRSTL
RST
0.2 VCC
(4) Power-on reset
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Symbol Pin Condition Value Min 2 Max Unit Remarks VCC is less than 0.2 V before power is turned on.
Parameter
Power rising time
tR
VCC
VCC = 3.3 V
20
ms
Power supply cutoff time
tOFF
VCC
ms
tR
VCC
0.9 VCC 0.2 V tOFF
Sudden change of power supply voltage may activate the power-on reset function. To change the power supply voltage while the device is in operation, it is recommended to rise the voltage smoothly to suppress fluctuations as shown below.
3.3 V VCC 3.0 V
RAM data hold
VSS
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
VCC RST
tRSTL
When power is turned on, it must be started while the RST pin is set to "L" level, after which wait for tRSTL and change the level to "H" once the Vcc power level is reached.
30
MB91126
(5) Normal Bus Access Read/Write Operation
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Condition Value Min Max 15 15 15 15 15 15 15 15 3 / 2 x tCYC - 25 tCYC - 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns * * Remarks
Parameter CS0 to CS5 delay time Address delay time Data delay time RD delay time WR0, WR1 delay time Valid address valid data input time RD valid data input time Data set up RD time RD Data hold time
Symbol tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV tDSRH tRHDX
Pin CLK, CS0 to CS5 CLK, A24 to A00 CLK, D31 to D16 CLK, RD CLK, WR0, WR1 A24 to A00, D31 to D16
RD, D31 to D16
25 0
* : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tcyc x the number of cycles added for the delay) to this rating.
31
MB91126
tCYC 2.4 V 0.8 V tCHCSL 2.4 V 0.8 V tCHCSH 2.4 V 2.4 V
CLK
CS0 to CS5
tCHAV
0.8 V
2.4 V
2.4 V 0.8 V tCLRH 2.4 V tRLDV tAVDV tDSRH Read tRHDX 2.4 V 0.8 V
A24 to A00
0.8 V tCLRL
RD
D31 to D16
CLK
2.4 V 0.8 V tCLWL 0.8 V tCLWH 2.4 V
WR (WR0 to WR1)
2.4 V
2.4 V 0.8 V
A24 to A00
0.8 V tCHDV 2.4 V
D31 to D16
0.8 V
write data
2.4 V 0.8 V
32
MB91126
(6) Timeshared Bus Access Read/Write Operations
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Value Min Max 10 10 15 15 15 15 10 10 10 10 tCYC - 25 Unit ns ns ns ns ns ns ns ns ns * Remarks
Parameter ALE delay time CS1 delay time Address delay time Data delay time RD delay time WR0, WR1 delay time WR0, WR1 pulse width RD valid data input time Data set up RD time RD Data hold time
Symbol tCLLH2 tCLLL2 tCHCSL2 tCHCSH2 tCHAV2 tCHDV2 tCLRL2 tCLRH2 tCLWL2 tCLWH2 tRLDV2 tDSRH2 tRHDX2
Pin CLK, ALE CLK, CS1 CLK, D31 to D16 CLK, RD CLK, WR0, WR1
Condition
RD, D31 to D16
25 0
* : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tcyc x the number of cycles added for the delay) to this rating.
33
MB91126
tCYC MA1 MA2 2.4 V 0.8 V tCLLH2 0.8 V tCLLL2 2.4 V 2.4 V 0.8 V 0.8 V BA1 BA2 2.4 V 2.4 V
CLK
ALE
tCHCSL2
0.8 V tCHCSH2 2.4 V
CS1
0.8 V
At reading D31 to D16 MP bus
tRLDV2 2.4 V 0.8 V tCHAV2
tDSRH2
tRHDX2 2.4 V 0.8 V
Address
2.4 V 0.8 V
2.4 V 0.8 V
Read
RD
tCLRL2
2.4 V 0.8 V tCLRH2
At writing D31 to D16 MP bus
2.4 V 0.8 V tCHAV2
Address
tCHDV2
2.4 V 0.8 V
Write
WR0, WR1
tCLWL2
2.4 V 0.8 V tCLWH2
A15 to A08 At non multiplier
2.4 V 0.8 V tCHAV2
34
MB91126
(7) Ready Input Timing
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Symbol tRDYS tRDYH Pin CLK, RDY CLK, RDY Condition Value Min 15 0 ns Max Unit ns Remarks
Parameter RDY setup time CLK CLK RDY hold time
tCYC
2.4 V
2.4 V 0.8 V 0.8 V
CLK
tRDYS
tRDYH
tRDYS tRDYH
RDY
If "wait" is executed
0.8 V
2.4 V
RDY
If "wait" is not executed
2.4 V
0.8 V
35
MB91126
(8) Holding Timing
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Symbol tCHBGL tCHBGH tXHAL tHAHV Pin CLK, BGRNT BGRNT Condition Value Min tCYC - 10 tCYC - 10 Max 10 10 tCYC + 10 tCYC + 10 Unit ns ns ns ns Remarks
Parameter BGRNT delay time Pin floating BGRNT time BGRNT Pin valid time
Note : More than one cycle is required for BGRNT to change after BRQ is input.
tCYC
2.4 V
2.4 V
2.4 V
2.4 V
CLK
BRQ
tCHBGL tCHBGH 2.4 V 0.8 V tXHAL tHAHV
BGRNT
Pin
High-Z
36
MB91126
(9) UART Timing
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX tBUSY tCLZO tCLSL tCHOZ Pin External shift clock mode Internal shift clock mode Condition Value Min 8 tCYCP* - 10 50 50 4 tCYCP* - 10 4 tCYCP* - 10 0 50 50 50 Max + 50 50 6 tCYCP* 50 3 tCYCP* Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
Parameter Serial clock cycle time SCK SO delay time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO delay time Valid SI SCK SCK valid SI hold time Serial busy time SCS SCK, SO delay time SCS SCK input mask time SCS SCK, SO High-Z time
* : tCYCP : Peripheral clock cycle time
37
MB91126
Internal shift clock mode
tSCYC
SCK
tSLOV
SO SI
tIVSH tSHIX
External shift clock mode
tCLZO
tSLSH
tSHSL
tBUSY
tCHOZ
SCK
tSLOV
SO SI
tIVSH tSHIX
SCS
tCLSL
38
MB91126
(10) Trigger Input Timing
(VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = -30 C to +70 C) Pin INT0 to INT5 Condition Value Min 5 tCYCP* Max Unit ns Remarks
Parameter Input pulse width
Symbol tTRGH tTRGL
* : tCYCP : Peripheral clock cycle time
INT0 to INT5
tTRGH tTRGL
39
MB91126
s EXAMPLE CHARACTERISTICS
(1) "H" level output voltage Ta = +25 C
Output "H" voltage (VOH) example characteristics
3.8
(2) "L" level output voltage Ta = +25 C
Output "L" voltage (VOL) example characteristics
0.5
Output voltage (V)
3.4 3.2 3 2.8 2.6 2.8
Output voltage (V)
3.6
0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 2.8
3
3.2
3.4
3.6
3.8
3
3.2
3.4
3.6
3.8
Power supply voltage (V)
Power supply voltage (V)
(3) Power supply current Ta = +25 C
Power supply current (ICC) example characteristics
100
(4) Power supply current at sleep mode Ta = +25 C
Power supply current (ICCS) example characteristics
100 90 80 70 60 50 40 30 20 10 0 2.8
fcp = 25 MHz fcp = 20 MHz fcp = 12.5 MHz
Power supply current (mA)
60 50 40 30 20 10 0 2.8
fcp = 25 MHz fcp = 20 MHz fcp = 12.5 MHz
Power supply current (mA)
90 80 70
3
3.2
3.4
3.6
3.8
3
3.2
3.4
3.6
3.8
Power supply voltage (V)
Power supply voltage (V)
(5) Power supply current at stop mode Ta = +25 C
Power supply current (ICCH3) example characteristics
100
Power supply current (A)
90 80 70 60 50 40 30 20 10 0 2.8
3
3.2
3.4
3.6
3.8
Power supply voltage (V)
40
MB91126
s ORDERING INFORMATION
Part number MB91126 Package 100-pin Plastic LQFP (FPT-100P-M05) Remarks
41
MB91126
s PACKAGE DIMENSION
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
* 14.000.10(.551.004)SQ
75 51
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
76
50
0.08(.003) Details of "A" part
INDEX
1.50 -0.10 .059 -.004 (Mounting height)
26
+0.20
+.008
100
0.100.10 (.004.004) (Stand off) 0.25(.010)
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
1
25
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
0.1450.055 (.0057.0022)
C
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches) Note : The values in parentheses are reference values.
42
MB91126
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0303 (c) FUJITSU LIMITED Printed in Japan

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